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nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 1 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. feature cas latency frequency speed bins -3c/3ci (ddr2-667-cl5) -ac/aci/acl (ddr2-800-cl5) -be (ddr2-1066-cl7) -bd (ddr2-1066-cl6) units parameter min. max. min. max. min. max. min. max. tck (avg.) clock frequency 125 333 125 400 125 533 125 533 mhz trcd ? 15 - 12.5 - 12.5 - 11.25 - ns trp ? 15 - 12.5 - 12.5 - 11.25 - ns trc ? 60 - 57.5 - 57.5 - 56.25 - ns tras ? 45 70k 45 70k 45 70k 45 70k ns tck (avg.) @ cl3 ? 5 8 5 8 5 8 5 8 ns tck (avg.) @ cl4 3.75 8 3.75 8 3.75 8 3.75 8 ns tck (avg.) @ cl5 3 8 2.5 8 2.5 8 2.5 8 ns tck (avg.) @ cl6 - - 2.5 8 2.5 8 1.875 8 ns tck (avg.) @ cl7 - - - - 1.875 8 1.875 8 ns z 1.8v 0.1v power supply voltage z 8 internal memory banks z programmable cas latency: 3, 4, 5 (ddr2-3c/-3ci/-ac/-aci/-acl) 6 (-bd), 7 (-be) z programmable additive latency: 0, 1, 2, 3, 4 5 z write latency = read latency -1 z programmable burst length: z 4 and 8 programmable sequential / interleave burst z ocd (off-chip driver impedance adjustment) z odt (on-die termination) z 4n-bit prefetch architecture z data-strobes: bidi rectional, differential z support industrial grade temperature -40 ~95 operating temperature (-3ci/-aci) z 1kb page size for x4 and x8 2kb page size for x16 z strong and weak strengt h data-output driver z auto-refresh and self-refresh z power saving power-down modes z 7.8 s max. average periodic refresh interval z rohs compliance z packages: z 60-ball bga for x4 / x8 components z 84-ball bga for x16 components
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 2 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. description the 1giga bit (1gb) double-data-rate-2 (ddr2) drams is a high-speed cmos double data rate 2 sdram containing 1,073,741,824 bits. it is inter nally configured as an octal-bank dram. the 1gb chip is organized as 32mbit x 4 i/o x 8 banks, 16m bit x 8 i/o x 8 bank or 8mbit x 16 i/o x 8 bank device. these synchronous devices achieve high speed double-data-rate tr ansfer rates of up to 1066 mb/sec/pin for general appli- cations. the chip is designed to comply with all key ddr2 dram key features: (1) posted cas with additive latency, (2) write latency = read latency -1, (3) normal and weak str ength data-output driver, (4) variable data-output impedance adjustment and (5) an odt (on- die termination) function. all of the control and addres s inputs are synchronized with a pair of exter nally supplied differential clocks. inputs are latched at the cross point of di fferential clocks (ck rising and ck falling). all i/os are synchr onized with a single ended dqs or differential dqs pair in a source synchronous fash ion. a 13 bit address bus for x4/x8 organized components and a 12 bit address bus for x16 component is used to convey row, column, and bank address devices. these devices operate with a single 1.8v 0.1v po wer supply and are available in bga packages.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 3 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. pin configuration ? 60 balls bga package (x4) < top view> see the balls through the package ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 4 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. pin configuration ? 60 balls bga package (x8) < top view> see the balls through the package a b c d e f g x 8 1 vdd dq4 nu,/rdqs vssq dq1 vssq vref cke a10/ ap 2 vss dm/rdqs vddq dq3 vss we ba 1 3 7 8 9 a3 vddq vdd dqs vssq dq0 vssq ck ck cs vssq dqs vddq vssdl ras cas vdd h j k l dq6 vddq vddl a7 a12 vdd ba0 a1 a5 a9 nc nc a11 a6 a2 dq2 a13 a8 a4 a0 dq7 vddq dq5 vss ba2 vss odt ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 5 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. pin configuration ? 84 balls bga package (x16) < top view> see the balls through the package ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 6 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. input / output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all addre ss and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactiva tes, internal clock signals and device input buffers and output drivers. taking ck e low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit and for self-refresh entry. cke is asynchronous for self-refresh exit. after v ref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self-refresh entry and exit, v ref must maintain to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power down. input buffers, excluding cke, are disabled during self-refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on systems with multiple memory ranks. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm, ldm, udm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data durin g a write access. dm is sampled on both edges of dqs. although dm pins are input only, t he dm loading matches the dq and dqs loading. for x8 device, the function of dm or rdqs / rqds is enabled by emrs command. ba0 - ba2 input bank address inputs: ba0, ba1, and ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0 ? a13 input address inputs: provides the row address for activa te commands and t he column address and auto precharge or read/write commands to select one location out of the memory array in the respective bank. a10 is sampled during a pr echarge command to determine whether the precharge applies to one bank (a10=low) or all banks (a10=high). if only one bank is to be precharged, the bank is selected by ba0-ba2. th e address inputs also provide the op-code during mode register set commands.a13 row address use on x8 components only. dq input/output data inputs/output: bi-directional data bus. dqs, ( dqs ) ldqs, ( ldqs ), udqs,( udqs ) input/output data strobe: output with read data, input with write data. edge aligned with read data, centered with write data. for the x16, ldqs corresponds to the data on dq0 - dq7; udqs corresponds to the data on dq8-dq15. the data strobes dqs, ldqs, udqs, and rdqs may be used in single ended mode or paired with the optional complementary signals dqs , ldqs , and udqs to provide differential pair signaling to the system during bo th reads and writes. an emrs(1) control bit enables or disables the comp lementary data strobe signals.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 7 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. symbol type function rdqs, ( rdqs ) input/output read data strobe: for x8 components a rdqs and rdqs pair can be enabled via emrs(1) for real timing. rdqs and rdqs is not support x16 components. rdqs and rdqs are edge-aligned with real data. if enable rdqs and rdqs then dm function will be disabled. odt input on die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is applied to each dq, dqs, dqs , rdqs, rdqs , and dm signal for x8 configuration. for x16 configurat ion odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal. the odt pin will be ignored if the emrs (1) is programmed to disable odt. nc no connect: no internal electric al connection is present. v ddq supply dq power supply: 1.8v 0.1v v ssq supply dq ground v ddl supply dll power supply: 1.8v 0.1v v ssdl supply dll ground v dd supply power supply: 1.8v 0.1v v ss supply ground v ref supply sstl_1.8 reference voltage
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 8 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. ordering information green note: nt5tu64m16gg-acl is idd 6 < 6 ma. standard grade speed part number package clock (mhz) cl-t rcd -t rp nt5tu256m4ge ? 3c 333 5-5-5 nt5tu256m4ge ? ac 400 5-5-5 nt5tu128m8ge ? 3c 333 5-5-5 nt5tu128m8ge ? ac 400 5-5-5 nt5tu128m8ge ? be 533 7-7-7 nt5tu128m8ge ? bd 60-ball bga 533 6-6-6 nt5tu64m16gg ? 3c 333 5-5-5 nt5tu64m16gg ? ac 400 5-5-5 nt5tu64m16gg ? acl* 400 5-5-5 nt5tu64m16gg ? be 533 7-7-7 organization nt5tu64m16gg ? bd 84-ball bga 533 6-6-6 industrial grade speed part number package clock (mhz) cl-t rcd -t rp nt5tu128m8ge ? 3ci 333 5-5-5 nt5tu128m8ge ? aci 60-ball bga 400 5-5-5 nt5tu64m16gg ? 3ci 333 5-5-5 organization nt5tu64m16gg ? aci 84-ball bga 400 5-5-5
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 9 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. block diagram (256mb x 4) address register row-address mux refresh counter read latch drivers receivers odt control
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 10 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. block diagram (128mb x 8) address register row-address mux refresh counter read latch drivers receivers odt control
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 11 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. block diagram (64mb x 16)
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 12 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. functional description the 1gb ddr2 sdram is a high-speed cmos, dynamic rand om-access memory containing 1,073,741,824 bits. the 1gb ddr sdram is internally configured as an octal-bank dram. read and write accesses to the ddr2 sdra m are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. accesses begin with the registration of an activate command, which is followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accesses (ba0, ba1, & ba2 select the banks, a0-a13 select the row for x4 and x8 components, a0-a12 select the row for x16 components). the addr ess bits registered coincident with the read or write command are used to select the starting column location fo r the burst access and to determine if the auto-precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialize d. the following sections provide detailed information covering device initialization, register defini tion, command description and device operation. power-up and initialization ddr2 sdrams must be powered up and initialized in a predefin ed manner. operational proc edures other than those specified may result in undefined operation. the following sequence is required for power up and initialization. 1. either one of the following s equence is required for power-up. while applying power, attempt to maintain cke below 0.2 x v ddq and odt at a low state (all other inputs may be unde- fined) the vdd voltage ramp time must be no greater than 200ms from when vdd ramps from 300mv to vdd min; and during the vdd voltage ramp up, ivdd-vddqi Q 0.3 volts. once the ramp ing of the supply voltages is complete (when vddq crosses vddq min), the supply voltage specificat ions in re-commanded dc operating conditions table. - vdd, vddl, and vddq are driven from a signal power converter output, and - vtt is limited to 0.95v max, and - vref tracks vddq/2; vref must be within 300mv wi th respect to vddq/2 during supply ramp time. - vddq>=vref must be met at all times. while applying power, attempt to maintain cke below 0.2 x vddq and odt at a low stat e, all other inputs may be undefined, voltage levels at i/os and out puts must be less than vddq during voltage ramp time to avoid dram latch-up. during the ramping of the supply voltages, vdd R vddl R vddq must be maintained and is applicable to both ac and dc levels until the ramping of the supply voltages is complete, which is when vddq crosses vddq min. once the ramping of the supply voltages is complete, the supply voltage specifications provided in re-commanded dc operating conditions table. - apply vdd/vddl before or at the same time as vddq. - vdd/vddl voltage ramp time must be no greater th an 200ms from when vdd ramps from 300mv to vddmin. - apply vddq before or at the same time as vtt.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 13 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. - the vddq voltage ramp time from when vdd min is ac hieved on vdd to when vddq min is achieved on vddq must be no greater than 500ms. (note: while vdd is ramping, current may be supplied from vdd through the dram to vddq.) - vref must track vddq/2; vref must be within 300m v with respect to vddq/2 during supply ramp time. - vddq R vref must be met at all time. - apply vtt. 2. start clock (ck, ck ) and maintain stable condition. 3. for the minimum of 200us after stable power (vdd, vddl, vddq, vref, and vtt are between their minimum and maximum values as stated in re-commanded dc operating conditions table, and stabl e clock, then apply nop or deselect & take cke high. 4. waiting minimum of 400ns then issue pre-charge all command. nop or deselect applied during 400ns period. 5. issue an emrs command to emr (2). (pro vide low to ba0 and ba2, and high to ba1). 6. issue an emrs command to emr (3). (pro vide low to ba2 and high to ba0 and ba1). 7. issue emrs to enable dll. (provide low to a0, high to ba0 and low to ba1-ba2 and a13-a15. and a9=a8=a7=low must be used when issuing this command.) 8. issue a mode register set command for dll reset. (provide high to a8 and low to ba0-ba2, and a13-a15.) 9. issue a precharge all command. 10. issue 2 more auto-refresh commands. 11. issue a mrs command with low to a8 to initialize devi ce operation (i.e. to program operating parameters without resetting the dll.) 12. at least 200 clocks after step 7, ex ecute ocd calibration (off chip driver impedance adjustment). if ocd calibration is not used, emrs to emr (1) to set ocd calibration default (a9=a8=a7=high) followed by emrs to emr (1) to exit ocd calibration mode (a9=a8=a7=low) must be issued with other operating parameters of emr (1). 13. the ddr2 dram is now ready for normal operation. * to guarantee odt off, vref must be valid and a low level must be applied to the odt pin. example ck, ck 1st auto refresh mrs pre all emrs cmd 2nd auto refresh trp trp trfc trfc extended mode register set with dll enable mode register set with dll reset pre all tmrd tmrd min. 200 cycles to lock the dll cke command 400 ns mrs nop tmrd emrs follow ocd flowchart odt "low" follow ocd flowchart emrs
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 14 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. register definition programming the mode registrati on and extended mode registers for application flexibility, burst length, burst type, cas latency, dll reset function, write recovery time (twr) are user defined variables and must be programmed with a mode register set (mrs) command. additionally, dll disable function, additive cas latency, driver impedance, odt (on die termi nation), single-ended strobe and ocd (off chip driver impedance adjustment) are also user defined variables and must be programmed with an extended mode register set (emrs) command. contents of the mode register (mr) and extended mode registers (emr (#)) can be altered by re-executing the mrs and emrs commands. if the user chooses to modify only a subset of the mrs or emrs variables, all variables must be redefined when the mrs or emrs co mmands are issued. mrs, emrs and dll reset do not affect array contents, which mean re-initializat ion including those can be executed any time after power-up without affecting array contents. mode registration set (mrs) the mode register stores the data for controlling the various operat ing modes of ddr2 sdram. it controls cas latency, burst length, burst sequence, test mode, dll reset, twr and various vendor specific options to make ddr2 sdram useful for various applications. the default value of the mode register is not defined , therefore the mode register must be written after power-up for proper operation. the mode register is written by asserting low on cs , ras , cas , we , ba0 and ba1, while controlling the state of address pins a0 ~ a13. the ddr2 sdram should be in all banks precharged (idle) mode with cke already high prior to writing into the m ode register. the mode register set command cycle time (t mrd ) is required to complete the write operation to the mode regi ster. the mode register cont ents can be changed using the same command and clock cycle requirements during normal operatio n as long as all banks are in the precharged state. the mode register is divided into various fields depending on f unctionality. burst length is defined by a0 ~ a2 with options of 4 and 8 bit burst length. burst address sequence type is defined by a3 and cas latency is defined by a4 ~ a6. a7 is used for test mode and must be set to low for normal mrs oper ation. a8 is used for dll reset. a9 ~ a11 are used for write recovery time (wr) definition for auto-precharge mode.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 15 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. mrs mode register operation table (address input for mode set) a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ba0 ba1 ba2 address field bl a0 a1 a2 4 0 1 0 8 1 1 0 burst length burst type a3 sequential 0 interleave 1 burst type cas latency a4 a5 a6 reserved 0 0 0 reserved 1 0 0 / cas latency 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 6 reserved 7 mrs mode ba0 ba 1 mr 0 0 emr(1) 1 0 mrs mode 0 1 1 1 emr(3) emr (2) active power down exit time a1 2 fast exit (use txard) 0 slow exit (use txards) 1 active power down exit time ** wr (cycles) a9 a10 a11 reserved 0 0 0 2 1 0 0 write recovery for autoprecharge 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 4 5 6 7 3 dll reset a8 no 0 yes 1 dll reset mode a7 normal 0 test 1 mode * ba2 and a13 are reserved for future use and must be set to "0" when programming mr. 3 4 5 ddr2-1066 ddr2-667 ddr2-800 8
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 16 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. extended mode register set -emrs (1) programming a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ba0 ba1 ba2 address field dll enable a0 enable 0 disable 1 dll output driver impedance control a1 full strength 0 reduced strength 1 d.i.c rtt (nominal) a2 a6 odt disabled 0 0 75 ohm 1 0 rtt 0 1 1 1 50 ohm *2 150 ohm mrs mode ba0 ba1 mr 0 0 emr(1) 1 0 mrs mode 0 1 1 1 emr(3) emr(2) qoff ** dqs a10 enable 0 disable 1 dqs * ba2 and a13 are reserved for future use and must be set to 0 when programming the emr(1). *2 mandatory for ddr2-1066 *3 when adjust mode is issued, al from previously set value must be applied. *4 after setting to default, ocd calibration mode needs to be exited by settin ga9-a7 to 000. *5 output disabled ? dqs, dqss, dqss, rdqs, rdqs. this feature is used in conjunction with dimm idd measurements when iddq is not desired to be included. *6 if rdqs is enabled, the dm function is disabled. rdqs is active for reads and do not care for writes. additive latency a3 a4 a5 0 0 0 0 1 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 3 4 6 2 reserved additive latency 5 qoff *5 a12 output buffer enabled 0 output buffer disabled 1 rdqs enable*6 a11 enable 0 disable 1 rdqs ocd calibration program a7 a8 ocd calibration mode exit; maintain setting 0 0 drive(1) 1 0 0 1 0 0 adjust mode *3 drive(0) a9 0 0 0 1 1 1 ocd calibration default*4 1 ocd program ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 17 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. extended mode register set ?emrs (1) the extended mode register emrs(1) stores the data for enabling or disabling the dll, output driver strength, additive latency, odt, dqs disable, ocd program, rqds enabl e. the default value of the exte nded mode register emrs (1) is not defined, therefore t he extended mode register must be written a fter power-up for proper operation. the extended mode register is written by asserting low on cs , ras , cas , we , ba1 and high on ba0, while c ontrolling the state of the address pins. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the emrs (1). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in prechar ge state. a0 is used for dll enable or disable. a1 is used for enabling a half strength output driver. a3-a5 determines the additive lat ency, a7-a9 are used for ocd control, a10 is used for dqs disable and a11 is used for rdqs enable. a2 and a6 are used for odt setting. single-ended and differential data strobe signals the following table lists all possible combinations for dqs, dqs , rdqs, rdqs which can be programmed by a10 & a11 address bits in emrs(1). rdqs and rdqs are available in x8 components only. if rdqs is enabled in x8 components, the dm function is disabled. rdqs is active for reads and don?t care for writes. emrs (1) strobe function matrix a11 (rdqs enable) a10 ( dqs enable) rdqs/dm rdqs dqs dqs signaling 0 (disable) 0 (enable) dm hi-z dqs dqs differential dqs signals 0 (disable) 1 (disable) dm hi-z dqs hi-z single-ended dqs signals 1 (enable) 0 (enable) rdqs rdqs dqs dqs differential dqs signals 1 (enable) 1 (disable) rdqs hi-z dqs hi-z single-ended dqs signals dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self-refresh operation and is automatically re-enabled and reset upon exit of self-refresh operation. any time the dll is reset, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. less clock cycles may result in a violation of the t ac or t dqsck parameters. output disable (qoff) under normal operation, the dram outputs are enab led during read operation for driving data (q off bit in the emrs (1) is set to 0). when the q off bit is set to 1, the dram outputs will be disabled. disabling the dram outputs allows users to measure i dd currents during read operations, without including t he output buffer current and external load currents.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 18 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. emrs (2) extended mode register set programming address field extended mode register 1 pasr*** ba1 ba0 a11 a10a9a8a7a6a5a4a3a2a1a0 0* a2 a1 a0 partial array self refresh 000 full array 001 half array (ba[2:0]=000, 001, 010, &011) 010 quarter array (ba[2:0]=000&001) 011 1/8 th array (ba[2:0] = 000) 100 3 / 4 array (ba[2:0]=010,011,100,101,110, &111) 101 half array (ba[2:0]=100, 101, 110, & 111) 110 quarter array (ba[2:0]=110&111) 1111/8 th array (ba[2:0]=111) 0 srf a7 0 disable 1 enable** (85c tcase 95c) high temperature self-refresh rate enable a12 0* ba2 0* ba0 mrs mode 0mrs 1 emrs(1) ba1 0 0 1 1 1 0 emrs(2) emrs(3): reserved * the rest bits in emrs(2) is reserved for future use and all bits in emrs (2) except a0-a2,a7,ba0, and ba1 must be programmed to 0 when setting emrs(2) during initialization. ** ddr2 sdram module user can look at module spd field byte 49 bit [0]. *** optional. if pasr(partial array self refresh ) is enabled, data located in areas of the array beyond the spec. location will be lost if self refresh is entered . extended mode register set emrs (2) the extended mode registers (2) controls refresh related features. the default valu e of the extended mode register(2) is not defined, therefore the extended mode regi ster(2) is written by asserting low on cs, ras, cas, we, ba0, high on ba1, while controlling the states of address pin a0-a13. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register (2). the mode register set command cycle time (tmrd) must be satisfied to complete the write operation to the extended mode register (2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all ban ks are in the precharge state. emrs (3) extended mode register set programming all bits in emrs (3) expect ba0 and ba1 are reserved for future use and must be programmed to 0 when setting the mode register during initialization.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 19 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. off-chip driver (ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the flow chart below is an example of the sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be set before entering ocd impedance adjustment and odt (on die termination) should be carefully controlled depending on system environment. start emrs: drive (1) dq & dqs high; dqs low test emrs : enter adjus t mode bl=4 cod e inpu t to all dqs inc, dec, or nop emrs: drive(0) dq & dqs low; dqs high test emrs : enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: ocd calibration mode exit end all ok all ok need calibration emrs: ocd calibration mode exit mrs should be set before entering ocd impedance adjustment and odt should be carefully controlled depending on system environment emrs: ocd calibration mode exit emrs: ocd calibration mode exit emrs: ocd calibration mode exit emrs: ocd calibration mode exit need calibration
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 20 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. extended mode register set for ocd impedance adjustment ocd impedance adjustment can be done usi ng the following emrs (1) mode. in drive mode all outputs are driven out by ddr2 sdram and drive of rdqs is dependent on emrs (1) bit enabling rdqs operation. in dr ive (1) mode, all dq, dqs (and rdqs) signals are driven high and all dqs (and rdqs ) signals are driven low. in drive (0) mode, all dq, dqs (and rdqs) signals are driven low and all dqs (and rdqs ) signals are driven high. in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibra tion default, output driver characterist ics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. output driver characteristics for ocd calibration default are specified in the following table. ocd applies only to normal full strength output drive setting defined by emrs (1) and if half strength is set, ocd default driver char acteristics are not applicable. when ocd calibration adjust mode is used, ocd default output driver characterist ics are not applicable. after ocd calibration is completed or driver strength is set to defau lt, subsequent emrs(1) commands not intended to adjust ocd c haracteristics must specify a7~a9 as ?000? in order to maintain the default or calibrated value. off- chip-driver program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive(1) dq, dqs, (rdqs) high and dqs low 0 1 0 drive(0) dq, dqs, (rdqs) low and dqs high 1 0 0 adjust mode 1 1 1 ocd calibration default
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 21 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. ocd impedance adjust to adjust output driver impedance, controllers must issue the adjust emrs (1) command along with a 4 bit burst code to ddr2 sdram as in the following table. for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive the burst code to all dq s at the same time. dt0 is the table means all dq bits at bit time 0, dt1 at bit time 1, and so forth. the dr iver output impedance is adj usted for all ddr2 sdram dqs simultaneously and after ocd calibration, all dqs of a giv en ddr2 sdram will be adjusted to the same driver strength setting. the maximum step count for adjustment can be up to 16 and when the limit is reached, further increment or decrement code has no effect. the default setting may be any step within the maximum st ep count range. when adjust mode command is issued, al from previously set value must be applied. 4 bit burst code inputs to all dqs operation dt0 dt1 dt2 dt3 pull-up driver strength pull-down driver strength 0 0 0 0 nop (no operation) nop (no operation) 0 0 0 1 increase by 1 step nop 0 0 1 0 decrease by 1 step nop 0 1 0 0 nop increase by 1 step 1 0 0 0 nop decrease by 1 step 0 1 0 1 increase by 1 step increase by 1 step 0 1 1 0 decrease by 1 step increase by 1 step 1 0 0 1 increase by 1 step decrease by 1 step 1 0 1 0 decrease by 1 step decrease by 1 step other combinations reserved for proper operation of adjust mode, wl = rl - 1 = al + cl -1 clocks and t ds / t dh should be met as the following timing diagram. input data pattern for adjustment, dt0 ~ dt3 is fixed and not affected by mrs addressing mode (i.e. sequential or interleave).
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 22 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. ocd adjust mode ocd adjust mode ocd calibration mode exit emrs ck ck cmd nop nop nop nop nop wl dqs dq tds tdh dt0 dt1 dt2 dt3 dm emrs nop wr dqs
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 23 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. drive mode drive mode, both drive (1) and drive (0), is used for cont rollers to measure ddr2 sdram driver impedance before ocd impedance adjustment. in this m ode, all outputs are driven out t oit after ?enter drive mode? command and all output drivers are turned-off t oit after ?ocd calibration mo de exit? command as the following timing diagram. nop nop nop nop emrs(1) cmd dq_in nop dqs_in ck, ck emrs(1) nop enter drive mode ocd calibration mode exit nop dqs high & dqs low for drive(1), dqs low & dqs high for drive 0 dqs high for drive(0) dqs high for drive(1) toit toit ? on-die termination (odt) odt (on-die termination) is a feature t hat allows a dram to turn on/off termi nation resistance for each dq, dq, dqs, dqs , rdqs, rdqs , and dm signal for x8 configurations via the odt c ontrol pin. for x16 configuration odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal via the odt control pin. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resistance for any or all dram devices. the odt function can be used for all active and standby modes . odt is turned off and not supported in self-refresh mode. functional representation of odt dram input buffer input pin rval1 rval1 rval2 rval2 sw1 sw1 sw2 sw2 vddq vddq vssq vssq rval3 rval3 sw3 sw3 vddq vssq ? switch sw1, sw2, or sw3 is enabled by the odt pin. selection bet ween sw1, sw2, or sw3 is determined by ?rtt (nominal)? in emrs. termination included on all dqs, dm, dqs, dqs , rdqs, and rdqs pins .
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 24 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. odt related timings mrs command to odt update delay during normal operation the value of the effective terminat ion resistance can be changed with an emrs command. the update of the rtt setting is done between tmod, min and tmod, max, and cke must remain high for the entire duration of tmod window for proper operation. the timings are shown in the following timing diagram. cke rtt ck, ck t is cmd taofd emrs nop nop nop nop nop tmod, min tmod, max old setting updating new setting emrs command directed to emr(1), which updates the information in emr(1)[a6,a2], i.e. rtt(nominal) setting in this diagram is the register and i/o setting, not what is measured from outside. however, to prevent any impedance glitch on t he channel, the following conditions must be met. - taofd must be met before issuing the emrs command. - odt must remain low for the entire durati on of tmod window, until tmod, max is met. now the odt is ready for normal operation with the new setti ng, and the odt may be raised again to turn on the odt. following timing diagram shows the proper rtt update procedure. cke rtt ck, ck t is cmd taofd emrs nop nop nop nop tmod, max old setting new setting emrs command directed to emr(1), which updates the information in emr(1)[a6,a2], i.e. rtt(nominal) setting in this diagram is the register and i/o setting, not what is measured from outside. taond nop ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 25 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. odt ? on/off ? timings odt timing for active/standby mode rtt t is t is t is taond taofd(2. 5 tck) t-3 t-5 t-4 t-0 t-2 t-1 t-6 cke internal term res. odt ck, ck taon, min taon, max taof, min taof, max ?? odt timing for power-down mode t is t is taofpd,max rtt taonpd,min taofpd,min taonpd,max t5 t6 t4 t3 t2 t0 t1 cke dq odt ck, ck ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 26 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. bank activate command the bank activate command is issued by holding cas and we high plus cs and ras low at the rising edge of the clock. the bank addresses ba0 ~ ba2 are used to select the desir ed bank. the row addresses a0 through a13 are used to determine which row to activate in the selected bank for and x8 organized components. for x16 components row addresses a0 through a12 have to be applied. the bank activate command must be applied before any read or write operation can be executed. immediately af ter the bank active command, the ddr2 sdram can accept a read or write command (with or without auto-precharge) on the following cl ock cycle. if an r/w command is issued to a bank that has not satisfied the t rcdmin specification, then additive latency must be programmed into the device to delay the r/w command which is internally issued to the device. the additive latency value must be chosen to assure t rcdmin is satisfied. additive latencies of 0, 1, 2, 3, 4, 5, and 6 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , respectively. the minimum time interval between successive bank activate commands to the same bank is determined (t rc ). the minimum time interval between bank active commands , to other bank, is the bank a to bank b delay time (t rrd ). in order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices, certain restrictions on operati on of the 8 bank devices must be observed. there are two rules. one for restricting the number of sequential act commands that can be issued and another for allowing more time for ras precharge for a precharge all command. the rules are list as follow: * 8 bank device sequential bank activation restriction: no mo re than 4 banks may be activated in a rolling tfaw window. converting to clocks is done by dividing tfaw by tck and roundi ng up to next integer value. as an example of the rolling window, if (tfaw/tck) rounds up to 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued in clock n+1 through n+9. *8 bank device precharge all allowance: trp for a precharge all command for an 8 bank device will equal to trp+tck, where trp is the value for a single bank pre-charge. bank activate command cycle: t rcd = 3, al = 2, t rp = 3, t rrd = 2, t ccd = 2 address nop command t0 t2 t1 t3 t4 col. addr. bank a row addr. bank b col. addr. bank b internal ras-cas delay trcdmin. bank a to bank b delay trrd. activate bank b read a posted cas activate bank a read b posted cas read a begins row addr. bank a addr. bank a precharge bank a nop addr. bank b precharge bank b row addr. bank a activate bank a trp row precharge time (bank a) trc row cycle time (bank a) tn tn+1 tn+2 tn+3 act ras-ras delay trrd. tras row active time (bank a) additive latency al=2 ck, ck
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 27 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. read and write commands and access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting ras high, cs and cas low at the clock?s rising edge. we must also be defined at this time to determine whether the access cycle is a read operation ( we high) or a write operation ( we low). the ddr2 sdram provides a fast column access operation. a single read or write command will initiate a serial read or write op eration on successive clock cycles. the boundary of the burst cycle is restricted to specific segments of the page length. a new burst access must not interrupt the previous 4 bit burst operation in case of bl = 4 setting. however, in case of bl=8 setting, two cases of interrupt by a new burst access ar e allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundary respectively, and the minimum cas to cas delay (t ccd ) is minimum 2 clocks for read or write cycles. posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a re ad or write command to be issued immediately after the ras bank activate command (or any time during the ras to cas delay time, t rcd , period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is the sum of al and the cas latency (cl). therefore if a user chooses to issue a read/write command before the trcdmin, then al greater than 0 must be written into the emrs (1). the write latency (wl) is always defined as rl - 1 (read latency -1) where read latency is defined as the sum of additive latency plus cas latency (rl=al+cl). if a user chooses to issue a read command after the t rcdmin period, the read latency is also defined as rl = al + cl. example of posted cas operation: read followed by a write to the same bank: al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 4 dout0 dout1 dout2 dout3 cmd dq 0 2 34 5 6 7 89101112 -1 1 >=trcd al = 2 rl = al + cl = 5 cl = 3 wl = rl -1 = 4 din0 din1 din2 din3 postcas1 dqs, dqs activate read write bank a bank a bank a ck, ck
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 28 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. read followed by a write to the same bank: al = 0, cl = 3, rl = (al + cl) = 3, wl = (rl -1) = 2, bl = 4 ? activate bank a 0 2 34 5 6 7 89101112 -1 1 cmd dq >=trcd rl = al + cl = 3 wl = rl ? 1 = 2 postcas5 dqs, dqs read bank a din0 din1 din2 din3 dout0 dout1 dout2 dout3 write bank a ck, ck al=0 cl=3
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 29 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). the parameters that de fine how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, se quential address ordering is nibble based for ease of implementation. the burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (a3) of the mrs. seamless burst read or write oper ations are supported. interru ption of a burst read or write operation is prohibited, when burst length = 4 is programmed. for burst inte rruption of a read or write burst when burst length = 8 is used, see the ?burst interruption ?section of this datasheet. a burst stop command is not supported on ddr2 sdram devices. bust length and sequence burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 4 x 1 1 3, 0, 1, 2 3, 2, 1, 0 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 8 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 note: 1) page length is a function of i/o organization 64mb x 16 organization (ca0-ca9); page size = 2k byte; page length = 1024 128mb x 8 organization (ca0-ca9 ); page size = 1k byte; page length = 1024 256mb x 4 organization (ca0-ca9, ca11); page size = 1k byte; page length = 2048 2) order of burst access for sequential addressing is "nibble-based" and therefore different from sdr or ddr components
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 30 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. burst read command the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column addre ss for the burst. the delay fr om the start of the command until the data from the first ce ll appears on the outputs is equal to the value of the read latency (rl). the data strobe outpu t (dqs) is driven low one clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subsequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs). the al is defined by the extended mode register set (emrs (1)) basic burst read timing dqs, dqs dq dqs dqs t rpre t dqsqmax t rpst t dqsck t ac dout dout dout dout clk, clk clk clk t ch t cl t ck do-read t qh dqsqmax t qh t t lz t hz examples: burst read operation: rl = 5 (al = 2, cl = 3, bl = 4) nop nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop <= tdqsck cmd dq bread523 dqs, dqs post cas ck, ck
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 31 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. burst read operation: rl = 3 (al = 0, cl = 3, bl = 8) cmd nop nop nop nop nop nop dq's nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 3 cl = 3 nop <= tdqsck bread303 dqs, dqs dout a4 dout a5 dout a6 dout a7 ck, ck ? ? burst read followed by burst write: rl = 5, wl = (rl-1) = 4, bl = 4 the minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around time(trtw), which is 4 clocks in case of bl=4 operation, 6 clocks in case of bl=8 operation. ? nop posted cas write a nop nop nop nop nop read a posted cas t0 t1 dout a0 dout a1 dout a2 dout a3 rl = 5 nop cmd dq brbw514 tn-1 tn tn+1 tn+2 tn+3 tn+4 tn+5 din a0 din a1 din a2 din a3 dqs, dqs wl = rl - 1 = 4 trtw(read to write turn around time) ck, ck
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 32 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. seamless burst read operation: rl = 5, al = 2, cl = 3, bl = 4 nop nop nop nop nop nop nop read a post cas read b post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 rl = 5 al = 2 cl = 3 sbr523 cmd dq dqs, dqs ck, ck ? the seamless burst read operation?s supp orted by enabling a read command at ever y clock for bl=4 operation, and every 4 clock for bl=8 operation. this operation allows regardless of same or different banks as long as the banks activated. burst write command the burst write command is initiated by having cs, cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting colu mn address. write latency (wl) is defin ed by a read latency (rl) minus one and is equal to (al + cl -1). a data strobe signal (dqs) has to be driven low (preamble) a time twpre prior to the wl. the first data bit of the burst cycle must be ap plied to the dq pins at the first risi ng edge of the dqs follo wing the preamble. th e tdqss specification must be satisfied for write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is comp leted, which is 4 or 8 bit burst. when the burst has finished, any additional data supplied to the dq pins will be ignored. the dq signal is ignored a fter the burst write operation is complete. the time from the completion of the burst write to bank precharge is named ?write recovery time? (wr). ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the emrs ?enable dqs? mode bit; timing advant ages of differential mode are realized in system design. the method by which the ddr2 sdram pin timing measured is mode dependent. basic burst write timing dqs, dqs dqs dqs t dqsh t dqsl t wpre wpst t din din din din t ds t dh ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 33 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. example: burst write operation: rl = 5 (al = 2, cl = 3), wl = 4, bl = 4 nop nop nop nop nop precharge nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 4 bw543 cmd dq nop din a0 din a1 din a2 din a3 <= tdqss twr completion of the burst write dqs, dqs ck, ck ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 34 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. burst read followed by burst write: rl = 5, wl = (rl-1) = 4, bl = 4 the minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around time(trtw), which is 4 clocks in case of bl=4 operation, 6 clocks in case of bl=8 operation. burst write followed by burst read: rl = 5 (al = 2, cl = 3), wl = 4, twtr = 2, bl = 4 ? nop nop nop nop nop read a post cas bwbr cmd dq nop din a0 din a1 din a2 din a3 al=2 cl=3 nop nop twtr t0 t2 t1 t3 t4 t5 t6 t7 t8 t9 write to read = (cl - 1)+ bl/2 +twtr(2) = 6 dqs, dqs wl = rl - 1 = 4 rl=5 ck, ck ? the minimum number of clocks from the burst write comma nd to the burst read command is (cl - 1) +bl/2 + t wtr where t wtr is the write-to-read turn-around time t wtr expressed in clock cycles. the t wtr is not a write recovery time (t wr ) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array. seamless burst write operation: rl = 5, wl = 4, bl = 4 nop nop nop nop nop nop nop din a0 din a1 din a2 din a3 write a post cas wl = rl - 1 = 4 write b post cas din b0 din b1 din b2 din b3 t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq sbr dqs, dqs ck, ck ? the seamless burst write operation is supported by enabli ng a write command every bl / 2 number of clocks. this operation is allowed regardless of same or diffe rent banks as long as the banks are activated.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 35 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. write data mask one write data mask input (dm) pin for each 8 data bits (dq) will be supported on ddr2 sdrams, consistent with the implementation on ddr sdrams. it has identical timings on wr ite operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. dm of x4 and x16 bit organization is not used during read cycles. however, dm of x8 bit organization can be used as rdqs during read cycles by emrs (1) setting. write data mask timing dqs dqs , dqs dqs t dqsh t dqsl t wpre wpst t dq din din din din t ds dh t dm don't care ? burst write operation with data mask: rl = 3 (al = 0, cl = 3), wl = 2, t wr = 3, bl = 4 nop nop nop nop nop write a t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 2 dm cmd dq nop twr <= tdqss precharge bank a activate trp dqs, dqs dm din a0 din a1 din a3 din a2 ck, ck ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 36 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. burst interruption interruption of a read or write burst is prohibited fo r burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. a read burst of 8 can only be interrupted by another read command. read burst interruption by a write or precharge command is prohibited. 2. a write burst of 8 can only be in terrupted by another write command. wr ite burst interruption by a read or precharge command is prohibited. 3. read burst interrupt occur exactly two clocks afte r the previous read command. any other read burst interrupt timings are prohibited. 4. write burst interrupt occur exactly two clocks a fter the previous write co mmand. any other read burst interrupt timings are prohibited. 5. read or write burst interruption is allo wed to any bank inside the ddr2 sdram. 6. read or write burst with auto-precharge enabled is not allowed to be interrupted. 7. read burst interruption is allowed by a read with auto-precharge command. 8. write burst interruption is allowed by a write with auto-precharge command. 9. all command timings are referenced to burst length se t in the mode register. they are not referenced to the actual burst. for example, minimum read to precharge timi ng is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (which is s horter because of interrupt). minimum write to precharge timing is wl + bl/ 2 + t wr , where t wr starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 37 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. examples: read burst interrupt timing example: (cl = 3, al = 0, rl = 3, bl = 8) nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq rbi dqs, dqs read b nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout b4 dout b5 dout b6 dout b7 nop ck, ck ? write burst interrupt timing example: (cl = 3, al = 0, wl = 2, bl = 8) nop nop nop nop nop write a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq wbi dqs, dqs nop din a0 din a1 din a2 din a3 din b0 din b1 din b2 din b3 dout b4 din b5 din b6 din b7 nop write b ck, ck nop
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 38 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. precharge command the precharge command is used to precharge or cl ose a bank that has been activated. the precharge command is triggered when cs, ras and we are low and cas is high at the rising edge of the clock. the pre-charge command can be used to precharge each bank independently or all banks simultaneously. three address bits a10, ba0, ba1, and ba2 are used to defi ne which bank to precharge when the command is issued. bank selection for precharge by address bit a10 ba2 ba1 ba0 precharge bank(s) low low low low bank 0 only low low low high bank 1 only low low high low bank 2 only low low high high bank 3 only low high low low bank 4 only low high low high bank 5 only low high high low bank 6 only low high high high bank 7 only high don't care don't care don't care all banks burst read operation followed by a precharge minimum read to precharge command spacing to the sa me bank = al + bl/2 + max (rtp, 2) - 2 clocks. for the earliest possible precharge, the precharge command ma y be issued on the rising edge which is ?additive latency (al) + bl/2 clocks? after a read co mmand, as long as the minimum t ras timing is satisfied. the minimum read to precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a read to precharge command. this time is call trtp (r ead t o p recharge). for bl=4 this is the time from the actual read (al after the read command) to precharge command. for bl=8 this is the time from al + 2 clocks after the read to the precharge command.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 39 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. examples: burst read operation followed by precharge: rl = 4 (al = 1, cl = 3), bl = 4, t rtp Q 2 clocks nop precharge nop bank a activate nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p413 nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 1 cl = 3 rl = 4 >=tras cl = 3 >=trp dqs, dqs nop >=trc >=trtp ck, ck ? burst read operation followed by precharge: rl = 4 (al = 1, cl = 3), bl = 8, t rtp Q 2 clocks ? nop nop nop post cas read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p413(8) nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 1 cl = 3 rl = 4 >=tras cl = 3 dqs, dqs nop >=trc >=trtp dout a4 dout a5 dout a6 dout a7 precharge nop nop first 4-bit prefetch second 4-bit prefetch ck, ck ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 40 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. burst read operation followed by precharge: rl = 5 (al = 2, cl = 3), bl = 4, t rtp Q 2 clocks nop nop nop bank a activate nop nop post cas read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p523 nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 2 cl = 3 rl = 5 >=tras cl = 3 >=trp precharge dqs, dqs >=trc >=trtp ck, ck ? burst read operation followed by precharge: rl = 6, (al = 2, cl = 4), bl = 4, t rtp Q 2 clocks nop nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p624 nop al + bl/2 clocks dout a0 dout a1 dout a2 dout a3 al = 2 cl = 4 rl = 6 >=tras cl = 4 precharge a bank a activate dqs, dqs nop nop >=trc >=trtp ck, ck >=trp ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 41 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. burst read operation followed by precharge: rl = 4, (al = 0, cl = 4), bl = 8, t rtp > 2 clocks nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p404(8) nop al + bl/2 clks + 1 dout a0 dout a1 dout a2 dout a3 cl = 4 rl = 4 >=tras >=trp dqs, dqs nop >=trtp dout a4 dout a5 dout a6 dout a7 precharge nop bank a activate first 4-bit prefetch second 4-bit prefetch ck, ck burst write followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + t wr . for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. this delay is known as a write recovery time (t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay, as ddr2 sdram does not support any burst interrupt by a precharge command. t wr is an analog timing parameter (see the ac table in this datasheet) and is not the programmed value for t wr in the mrs. examples: burst write followed by precharge : wl = (rl - 1) = 3, bl = 4, t wr = 3 nop nop nop nop nop write a post cas t 0 t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 wl = 3 bw-p3 cmd dq nop din a0 din a1 din a2 din a3 >=twr completion of the burst write precharge a nop dqs, dqs ck, ck
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 42 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. burst write followed by precharge : wl = (rl - 1) = 4, bl = 4, t wr = 3 nop nop nop nop nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = 4 bw-p4 cmd dq nop din a0 din a1 din a2 din a3 twr completion of the burst write precharge a nop dqs, dqs ck, ck ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 43 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. auto-precharge operation before a new row in an active bank can be opened, the acti ve bank must be precharged us ing either the pre-charge command or the auto-precharge function. when a read or a write command is given to the ddr2 sdram, the cas timing accepts one extra address, column address a10, to a llow the active bank to automat ically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst oper ation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is iss ued, then the auto-precharge function is enabled. during auto-precharge, a read command will execute as normal with t he exception that the active bank will begin to precharge internally on the rising edge which is cas latency (cl) clock cycles before the end of the read burst. auto-precharge is also implemented for write commands. the precharge operat ion engaged by the auto-precharge command will not begin until the last data of the writ e burst sequence is properly st ored in the memory array. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improving system performance for random data acce ss. the ras lockout circuit internally delays the precharge operation until the array restore operation has been complete d so that the auto-precharge command may be issued with any read or write command. burst read with auto-precharge if a10 is high when a read command is issued, the read with auto-precharge function is engaged. the ddr2 sdram starts an auto-precharge operation on the rising edge which is (al + bl/2) cycles later from the read with ap command if t ras (min) and t rtp are satisfied. if t ras (min) is not satisfied at the edge, the start point of auto -precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, the st art point of auto-precharge operation will be delayed until t rtp (min) is satisfied. in case the internal precharge is pushed out by t rtp , t rp starts at the point w here the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the mini mum time from read with auto-precharge to the next activate command becomes al + t rtp + t rp . for bl = 8 the time from read with auto-p recharge to the next activate command is al + 2 + t rtp + t rp . note that both parameters t rtp and t rp have to be rounded up to the next integer value. in any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. a new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) the ras precharge time (t rp ) has been satisfied from the clock at which the auto-precharge begins. (2) the ras cycle time (t rc ) from the previous bank activation has been satisfied.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 44 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. examples: burst read with auto-precharge followed by an activation to the same bank (t rc limit) rl = 5 (al = 2, cl = 3), bl = 4, t rtp Q 2 clocks nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5231 a10 ="high" trp auto-precharge begins dqs, dqs tras trcmin. nop al + bl/2 ck, ck ? burst read with auto-precharge followed by an activation to the same bank (tras limit): rl = 5 (al = 2, cl = 3), bl = 4, trtp Q 2 clocks nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5232 a10 ="high" trp auto-precharge begins dqs, dqs trc tras(min) nop ck, ck ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 45 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. burst read with auto-precharge followed by an activation to the same bank: rl = 4 ( al = 1, cl = 3), bl = 8, t rtp Q 2 clocks nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 al = 1 cl = 3 nop cmd dq br-ap413(8)2 a10 ="high" trp auto-precharge begins dqs, dqs nop dout a4 dout a5 dout a6 dout a7 first 4-bit prefetch second 4-bit prefetch >= trtp al + bl/2 ck, ck ? burst read with auto-precharge followed by an activation to the same bank: rl = 4 ( al = 1, cl = 3), bl = 4, t rtp > 2 clocks nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 al = 1 cl = 3 nop cmd dq br-ap4133 a10 ="high" auto-precharge begins dqs, dqs nop first 4-bit prefetch trtp al + trtp + trp trp ck, ck ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 46 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. burst write with auto-precharge if a10 is high when a write command is issued, the writ e with auto-precharge function is engaged. the ddr2 sdram automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (wr), programmed in the mrs register, as long as t ras is satisfied. the bank undergoing auto-precharge from the completion of the write burst may be reacti vated if the following two conditions are satisfied. (1) the last data-in to bank activate delay time (t dal = wr + t rp ) has been satisfied. (2) the ras cycle time (t rc ) from the previous bank activation has been satisfied. examples: burst write with auto-precharge (t rc limit): wl = 2, t dal = 6 (wr = 3, t rp = 3), bl = 4 nop nop nop nop nop bank a activate nop write w/ap t0 t2 t1 t3 t4 t5 t6 t7 nop cmd dq bw-ap223 a10 ="high" trp auto-precharge begins din a0 din a1 din a2 din a3 wl = rl-1 = 2 wr trcmin. dqs, dqs completion of the burst write tdal >=trasmin. ck, ck burst write with auto-precharge (t wr + t rp limit): wl = 4, t dal = 6 (t wr = 3, t rp = 3), bl = 4 nop nop nop nop nop bank a activate nop posted cas write w/ap 0 34567 t12 nop cmd dq bw-ap423 a10 ="high" trp auto-precharge begins din a0 din a1 din a2 din a3 wl = rl-1 = 4 twr >=trc t 9 8 completion of the burst write dqs, dqs tdal >=tras ck, ck ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 47 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. precharge & auto precharge clarification from command to command minimum delay between "from command" to "to command" units note precharge (to same bank as read) al + bl/2 + max(rtp,2) - 2 tck 1,2 read precharge all al + bl/2 + max(rtp,2) - 2 tck 1,2 precharge ( to same bank as read w/ap) al + bl/2 + max(rtp,2) - 2 tck 1,2 read w/ap precharge al al + bl/2 + max(rtp,2) - 2 tck 1,2 precharge (to same bank as write) wl + bl/2 + twr tck 2 write precharge al wl + bl/2 + twr tck 2 precharge (to same bank as write w/ap) wl + bl/2 + wr tck 2 write w/ap precharge al wl + bl/2 + wr tck 2 precharge (to same bank as precharge) 1 tck 2 precharge precharge al 1 tck 2 precharge 1 tck 2 precharge all precharge al 1 tck 2 note: 1) rtp [cycles] = ru {trtp (ns)/tck (ns)}, where ri stands for round up. 2) for a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or pre charge all, issued to that bank. the precharge period is satisfied after trp or trpall depending on the latest precharge command issue d to that bank. ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 48 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. refresh sdrams require a refresh of all rows in any rolling 64 ms inte rval. each refresh is generated in one of two ways: by an explicit auto-refresh command, or by an internally timed event in self-refresh mode. dividing the number of device rows into the rolling 64 ms interval defin ed the average refresh interval t refi , which is a guideline to controllers for distributed refresh timing. for example, a 1gbit ddr2 sdram has 8392 rows resulting in a t refi of 7.8 s. auto-refresh command auto-refresh is used during normal operat ion of the ddr2 sdrams. this command is no persistent, so it must be issued each time a refresh is required. the re fresh addressing is generated by the intern al refresh controller. this makes the address bits?don?t care? during an auto-refresh command. the ddr2 sdram requires auto-refresh cycles at an average periodic interval of t refi (maximum). when cs , ras and cas are held low and we high at the rising edge of the clock, the chip enters the auto-refresh mode. all banks of the sdram must be precharged and id le for a minimum of the precharge time (t rp ) before the auto-refresh command can be applied. an internal address counter supplies the addresses during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precha rged (idle) state. a delay between the auto-refresh command and the next acti vate command or subsequent auto-ref resh command must be greater than or equal to the auto-refresh cycle time (t rfc ). to allow for improved efficiency in scheduling and switching bet ween tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto-refresh commands c an be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 9 * t refi . t0 t2 t1 t3 ar ck, ck cmd precharge > = t rp nop auto refresh any nop > = t rfc > = t rfc auto refresh nop nop nop cke "high" ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 49 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. self-refresh command the self-refresh command can be used to retain data, even if the rest of the system is powered down. when in the self-refresh mode, the ddr2 sdram re tains data without external clocking. the ddr2 sdram device has a built-in timer to accommodate self-refresh operation. the self-refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. odt must be turned off before issuing self refresh command, by either driving odt pin low or using emrs (1) command. once the command is registered, cke must be held low to keep the device in self-refresh mode. when the ddr2 sdram has entered self-refresh mode all of the external c ontrol signals, except cke, are disabled. the clock is internally disabled during self-refresh operation to save power. the user may change the external clock frequency or halt the external clock one clock after self-refresh entry is registered, however, the clock must be restarted and stable before the device can exit self-refresh operation. once self -refresh exit command is registered , a delay equal or longer than the t xsnr or t xsrd must be satisfied before a valid command can be issued to the device. cke must remain high for the entire self-refresh exit period (t xsnr or t xsrd ) for proper operation. nop or deselect comm ands must be registered on each positiv e clock edge during the self-refresh exit interval. si nce the odt function is not supported durin g self-refresh operation, odt has to be turned off t aofd before entering self-refresh mode a nd can be turned on again when the t xsrd timing is satisfied. ck/ck t1 t3 t2 ck/ck may be halted ck/ck must be stable cke >=txsrd >= txsnr tn tr tm t5 t4 trp* tis taofd cmd self refresh entry nop non-read command read command t0 tis tis odt * device must be in theing "all banks idle" state to enter self refresh mode. * odt must be turned off prior to entering self refresh mode. * txsrd (>=200 tck) has to be satisfied for a read or as read with auto-precharge commend. * txsnr has to be satisfied for any command execept read or a read with auto-precharge command, where txsnr is defined as trfc + 10ns. * the minium cke low time is defined by the t ckemin. timming paramester. * since cke is an sstl input, v ref must maintained during self-refresh. ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 50 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. power-down power-down is synchronously entered when cke is register ed low, along with nop or deselect command. cke is not allowed to go low while mode register or extended mode regist er command time, or read or write operation is in progress. cke is allowed to go low while any other operation such as ro w activation, precharge, auto-precharge or auto-refresh is in progress, but power-down idd specification wi ll not be applied until finishing those operations. the dll should be in a locked state when power-down is en tered. otherwise dll should be reset after exiting power-down mode for proper read operation. if power-down occurs when all banks are precharged, this mode is referred to as precharge power-down ; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down . for active power-down two different power saving modes can be selected within the mrs regi ster, address bit a12. when a12 is set to ?low? this mode is referred as ?standard active power-down mode? and a fast power-down exit timing defined by the t xard timing parameter can be used. when a12 is set to ?high? this mode is referred as a power saving ?low power active power-down mode?. this mode takes longer to exit from the power-down mode and the t xards timing parameter has to be satisfied. entering power-down deactivates the input and output buffers , excluding ck, ck, odt and cke. also the dll is disabled upon entering precharge power-down or slow exit active power-d own, but the dll is kept enabled during fast exit active power-down. in power-down mode, cke low and a stable cl ock signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are ?don?t care?. power- down duration is limited by 9 times trefi of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid, executable command can be applied with power-down exit latency, t xp , t xard or t xards , after cke goes high. power-down exit latencies are defined in the ac spec table of this data sheet. power-down entry active power-down mode can be entered after an activate command. precharge power-down mode can be entered after a precharge, precharge-all or internal precharge command. it is also allowed to enter po wer-mode after an auto-refresh command or mrs / emrs (1) command when t mrd is satisfied. active power-down mode entry is prohibited as long as a read burst is in progress, meaning cke should be kept high until the burst operation is finished. theref ore active power-down mode entry after a read or read with auto-precharge command is allowed after rl + bl/2 is satisfied. active power-down mode entry is prohibited as long as a write burst and t he internal write recovery is in progress. in case of a write command, active power-down mode entry is allowed then wl + bl/2 + twtr is satisfied. in case of a write command with auto-p recharge, power-down mode entry is allowed after the internal precharge command has been executed, which wl + bl/2 + wr is starting from the write with auto-precharge command. in case the ddr2 sdram enters the precharge power-down mode .
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 51 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. examples: active power-down mode entry and exit after an activate command nop nop activate t0 t2 t1 cmd nop tn tn+1 cke active power-down entry nop nop act.pd 0 tis tn+2 tis active power-down exit valid command txard or txards *) ck, ck ? ? active power-down mode entry and exit after a read burst: rl = 4 (al = 1, cl =3), bl = 4 nop nop read t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 cl = 3 cmd dq dqs, dqs nop nop nop nop nop nop tn tn+1 cke al = 1 active power-down entry rl + bl/2 nop nop act.pd 1 tis tn+2 tis active power-down exit valid command txard or txards *) ck, ck read w/ap ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 52 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. active power-down mode entry and exit after a write burst: wl = 2, twtr = 2, bl = 4 nop nop write t0 t2 t1 t3 t4 t5 t6 t7 cmd dq dqs, dqs nop nop nop nop nop nop tn tn+1 cke wl = rl - 1 = 2 active power-down entry wl + bl/2 + twtr nop nop act.pd 2 twtr tis tn+2 tis valid command active power-down exit txard or txards *) ck, ck din a0 din a1 din a2 din a3 ? ? precharge power down mode entry and exit txp nop nop precharge *) t0 t2 t1 cmd nop nop tn tn+1 cke precharge power-down entry nop nop prepd tis tn+2 tis precharge power-down exit valid command trp nop t3 *) "precharge" may be an external command or an internal precharge following write with ap. ck, ck ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 53 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. no operation command the no operation command should be used in cases when the sdram is in an idle or a wait state. the purpose of the no operation command is to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminate a previ ous operation that is still executing, such as a bur st read or write cycle. deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don?t care. input clock frequency change during operation the dram input clock frequency can be changed under the following conditions: a) during self-refresh operation b) dram is in precharge power-down mode and odt is completely turned off. the ddr2-sdram has to be in precharged power-down mode and idle. odt must be already turned off and cke must be at a logic ?low? state. after a minimum of two clock cy cles after trp and taofd have been satisfied the input clock frequency can be changed. a stable new clock frequency has to be provided, before cke can be changed to a ?high? logic level again. after t xp has been satisfied a dll reset command via emrs (1) has to be issued. during the following dll re-lock period of 200 clock cycles, odt must remain off. after the dll-re-lock peri od the dram is ready to operate with the new clock frequency. example: input frequency change during precharge power-down mode nop nop t0 t2 t1 t3 t4 tx tx+1 ty cmd nop nop nop nop nop dll reset ty+2 ty+3 cke frequency change occurs here nop nop frequ.ch. tz txp stable new clock before power-down exit ck, ck trp taofd minimum 2 clocks required before changing the frequency ty+1 nop valid command 200 clocks odt is off during dll reset ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 54 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. asynchronous cke low event dram requires cke to be maintained ?high? for all valid oper ations as defined in this data sheet. if cke asynchronously drops ?low? during any valid operation dram is not guaranteed to preserve the contents of the memory array. if this event occurs, the memory controller must satisfy a time delay (tdelay ) before turning off the clocks. stable clocks must exist at the input of dram before cke is raised ?high? again. the dram mu st be fully re-initialized as described the the initialization sequence (section 2.2.1, step 4 thru 13). dram is ready for normal operation afte r the initialization sequence. see ac timing parametric table for t delay specification. asynchronous cke low event cke cke drops low due to an asynchronous reset event clocks can be turned off after this point tdelay ck, ck stable clocks ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 55 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. truth table command truth table cke function previous cycle current cycle cs ras cas we ba0-ba2 a13-a11 a10 a9 - a0 notes (extended) mode register set h h l l l l ba op code 1, 2 auto-refresh h h l l l h x x x x 1 self-refresh entry h l l l l h x x x x 1,8 self-refresh exit l h h x x x x x x x 1,7,8 single bank precharge h h l l h l ba x l x 1,2 precharge all banks h h l l h l x x h x 1 bank activate h h l l h h ba row address 1,2 write h h l h l l ba column l column 1,2,3 write with auto-precharge h h l h l l ba column h column 1,2,3 read h h l h l h ba column l column 1,2,3 read with auto-precharge h h l h l h ba column h column 1,2,3 no operation h x l h h h x x x x 1 device deselect h x h x x x x x x x 1 h x x x power down entry h l l h h h x x x x 1,4 h x x x power down exit l h l h h h x x x x 1,4 1. all ddr2 sdram commands are defined by states of cs , we , ras , cas , and cke at the rising edge of the clock. 2. bank addresses (bax) determine which bank is to be operated upon. for (e) mrs bax selects an (extended) mode register. 3. burst reads or writes at bl = 4 cannot be terminated. see sections "reads interrupted by a read" and "writes interrupted by a write" inspection for details. 4. the power down mode does not perform any refresh operations. t he duration of power down is therefore limited by the refresh requirements outlined. 5. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 6. x means "h or l (but a defined logic level)". 7. self refresh exit is asynchronous. 8. vref must be maintained during self refresh operation.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 56 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. clock enable (cke) truth table for synchronous transitions cke current state 2 previous cycle 1 (n-1) current cycle 1 (n) command (n) 3 ras , cas , we , cs action (n) 3 notes l l x maintain power-down 11, 13, 15 power-down l h deselect or nop power- down exit 4, 8, 11, 13 l l x maintain self refresh 11, 15, 16 self refresh l h deselect or nop self refresh exit 4, 5, 9, 16 bank(s) active h l deselect or nop active power-down entry 4,8,10,11,13 h l deselect or nop precharge power-down entry 4,8,10,11,13 all banks idle h l autorefresh self refresh entry 6, 9, 11,13 any state other than listed above h h refer to the command truth table 7 1. cke (n) is the logic state of cke at clock edge n; cke (n-1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr2 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n). 4. all states and sequences not shown are illegal or reserv ed unless explicitly described elsewhere in this document. 5. on self refresh exit deselect or nop commands must be iss ued on every clock edge occurring during the txsnr period. read com mands may be issued only after txsrd (200 clocks) is satisfied. 6. self refresh mode can only be entered from the all banks idle state. 7. must be a legal command as defined in the command truth table. 8. valid commands for power-down entry and exit are nop and deselect only. 9. valid commands for self refresh exit are nop and deselct only. 10. power-down and self refresh cannot be entered while read or write operations, (extended) mode register operations, precharg e or refresh operations are in progress. see section 2.8 "power down" and section 2.7.2 "self refresh command" for a detailed list of rest rictions. 11. minimum cke high time is 3 clocks, minimum cke low time is 3 clocks. 12. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 13. the power-down mode does not perform any refresh operations. the duration of power-down mode is therefore limited by the re fresh requirements. 14. cke must be maintained high while the device is in ocd calibration mode. 15. "x" means "don't care (incl uding floating around vref)" in self refresh and power down. however dt must be driven high or l ow in power down if the odt function is enabled (bit a2 or a6 set to "1" in mrs (1)). 16. vref must be maintained during self refresh operation
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 57 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. operating conditions absolute maximum dc ratings symbol parameter rating units notes v dd voltage on vdd pin relative to vss -1.0 to + 2.3 v 1,3 v ddq voltage on vddq pin relative to vss -0.5 to + 2.3 v 1,3 v ddl voltage on vddl pin relative to vss -0.5 to + 2.3 v 1,3 v in , v out voltage on any pin relative to vss -0.5 to + 2.3 v 1 t stg storage temperature -55 to + 100 1, 2 1. stresses greater than those listed under "absolut e maximum ratings" may cause permanent damage to the device. this is a stress rating onl y and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. 3. when vdd, vddq, and vddl are less than 500mv, vref may be equal to or less than 300mv. dram component operating temperature range symbol parameter rating units notes 0 to 85 (standard grade) 1, 2 t oper operating temperature - 40 to 95 (industrial grade) 1, 3 note: 1. operating temperature is the case surface temperature on the center/top side of the dram. 2. the operation temperature range is the temperature where all dram specification will be supported. outside of this temperatu re range, even if it is still within the limit of stress condition, some deviation on portion of operation specification may be required. during operation, the dram case tempera ture must be maintained between 0 -85 under all other specification parameter. however, in some applications, it is desirable to operate the dram up to 95 case temperature. therefore, two spec. may exist. supporting 0 -85 with full jedec ac & dc spec. this is the minimum requirements for all operating temperature options. this is an optional feature and not required. supporting 0 -85 and being able to extend to 95 with doubling auto-refresh command in frequency to a 32ms period (trfi=3.9 s) currently the period self-refresh interval is hard coded within the dram to a vendor specific value. there is a migration plan to support higher temperature self-refresh entry via the control of emrs (2) bit a7. 3. the operation temperature range is the temperature where all dram specification will be supported. outside of this temperatu re range, even if it is still within the limit of stress condition, some deviation on portion of operation specification may be required. during operation, the dram case tempera ture must be maintained between -40-95 under all other specification parameter. however, in some applications, it is desirable to operate the dram up to 105 degree c case temperature. therefore, two spec. may exist. supporting -40 -95 and being able to extend to 105
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 58 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. ac & dc operating conditions dc operating conditions recommended dc operating conditions (sstl_18) rating symbol parameter min. typ. max. units notes v dd supply voltage 1.7 1.8 1.9 v 1 v dddl supply voltage for dll 1.7 1.8 1.9 v 5 v ddq supply voltage for output 1.7 1.8 1.9 v 1,5 v ref input reference voltage 0.49 * v ddq 0.5 * v ddq 0.51 * v ddq v 2, 3 v tt termination voltage v ref - 0.04 v ref v ref + 0.04 v 4 1. v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. 2. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 3. peak to peak ac noise on v ref may not exceed +/- 2% v ref (dc). 4. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors is expected to be set equal to v ref and must track variations in die dc level of vref. 5. v ddq tracks with v dd , v ddl tracks with v dd . ac parameters are measured with v dd , v ddq , and v ddl tied together. odt dc electrical characteristic parameter / condition symbol min. nom. max. units notes rtt eff. impedance value for emrs(1)(a6,a 2)=0,1; 75 ohm rtt1(eff) 60 75 90 ohms 1 rtt eff. impedance value for emrs(1)(a6,a2)=0,1; 150 ohm rtt2(eff) 120 150 180 ohms 1 rtt eff. impedance value for emrs(1)(a6,a 2)=1,1; 50 ohm rtt3(eff) 40 50 60 ohms 1 deviation of vm with respect to vddq / 2 delta vm -6 6 % 2 1) measurement definition for rtt (eff): apply vihac and vilac to test pin separately, then measure current i (vihac) and i (vilac) respectively. rtt(eff) = (vihac - vilac) /( i(vihac) - i(vilac)) 2) measurement definition for vm: measure voltage (vm) at test pin (midpoint) with no load: delta vm =(( 2* vm / vddq) - 1 ) x 100%
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 59 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. dc & ac logic input levels ddr2 sdram pin timing are specified for either single end ed or differential mode depending on the setting of the emrs(1) ?enable dqs? mode bit; timing advantages of differ ential mode are realized in system design. the method by which the ddr2 sdram pin timing is measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossi ng at vref. in differential mode, these timing relationships are measured relative to the cross point of dqs and its complement, dqs. this di stinction in timing methods is guaranteed by design and characterization. in single ended mode, the dqs (and rdqs) signals are internally disabled and don?t care. single-ended dc & ac logic input levels ddr2-667/800/1066 symbol parameter min. max. units v ih (dc) dc input logic high vref + 0.125 vddq + 0.3 v v il (dc) dc input low -0.3 vref - 0.125 v v ih (ac) ac input logic high vref + 0.200 vddq+vpeak v v il (ac) ac input low vssq-vpeak vref - 0.200 v single-ended ac input test conditions symbol condition value units notes v ref input reference voltage 0.5 * v ddq v 1, 2 v swing(max) input signal maximum peak to peak swing 1 v 1, 2 slew input signal minimum slew rate 1 v / ns 3, 4 1. this timing and slew rate definition is valid for all single-ended signals except tis, tih, tds, and tdh. 2. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. 3. the input signal minimum slew rate is to be maintained over the range from v il(dc)max to v ih(ac)min for rising edges and the range from v ih(dc)min to v il(ac)max for falling edges as shown in the below figure. 4. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 60 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. differential dc and ac input and output logic levels symbol parameter min. max. units notes v id(ac) ac differential input voltage 0.5 vddq v 1 v ix(ac) ac differential cross point input voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 2 v ox(ac) ac differential cross point output voltag e 0.5 * vddq - 0.125 0.5 * vddq + 0.125 v 3 notes: 1) v id (ac) specifics the allowable dc execution of eac h input of differential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs, and udqs . 2) v ix (ac) specifices the input differential voltage lv tr-vcpl required for switching, where vtr is the true input (such as ck, dqs, ldqs , or udqs) level and vcp is the complementary input (such ck , dqs , ldqs , or udqs ) level. the minimum value is equal to v ih (dc) - v il (dc) . 3) the typical value of v ox (ac) is expected to be about 0.5v ddq of the transmitting device and v ox (ac) is expected to track variations in v ddq . v ox (ac) indicates the voltage at which differential signals must cross.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 61 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. output buffer levels output ac test conditions symbol parameter sstl-18 class ii units notes v otr output timing measurement re ference level 0.5 * vddq v 1 1. the vddq of the device under test is referenced. output dc current drive symbol parameter sstl-18 units notes i oh(dc) output minimum source dc curr ent, nominal -13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current, nominal 13.4 ma 2, 3, 4 1. v ddq = 1.7 v; v out = 1.42 v. (v out -v ddq ) / i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out / i ol must be less than 21 ohm for values of v out between 0v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh (dc) and i ol (dc) are based on the conditions given in note 1 and 2. th ey are used to test drive current capability to ensure v ihmin. plus a noise margin and v ilmax. minus a noise margin are delivered to an sst l_18 receiver. the actual current values are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement. ocd default setting table symbol description min. nominal max. unit notes - pull-up / pull down mismatch 0 - 4 ohms 6 - output impedance step size for oc d calibration 0 - 1.5 ohms 1,2,3 s out output slew rate 1.5 - 5 v / ns 1,4,5,7,8 1) absolute specification: t open ; v ddq = 1.8v 0.1v; vdd = 1.8v 0.1v. 2) impedance measurement condition for output source dc current: v ddq = 1.7v, v out = 1420 mv; (v out -v ddq )/i oh must be less than 23.4 ohms for values of v out between v ddq and v ddq -280mv. impedance measurement conditi on for output sink dc current: v ddq = 1.7 v; v out = -280mv; v out / i ol must be less than 23.4 ohms for values of v out between 0v and 280 mv. 3) mismatch is absolute value between pull-up and pull- down; both are measured at same temperature and voltage. 4) slew rates measured from v il (ac) to v ih (ac) with the load specified in section 8.2. 5) the absolute value of the slew rate as measured from dc to dc is equal to or grea ter than the slew rate as measured from ac to ac. this is guaranteed by des ign and characterization. 6) this represents the step size when the ocd is near 18 ohms at nominal conditions across a ll process parameters and represent s only the dram uncertainty. a 0 ohm value (no calibration) can only be achieved if the ocd impedance is 18 0.75 ohms under nominal conditions. 7) dram output slew rate specification applies to 533mt/s, 667mt/s, and 800mt/s speed pin. 8) timing skew due to dram output slew rate mis-match between dqs / dqs and associated dq's is included in tdqsq and tqhs specification.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 62 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. default output v-i characteristics ddr2 sdram output driver characteristics ar e defined for full strength default operati on as selected by the emrs (1) bits a7~a9 = ?111?. the driver characteristics evaluation conditions area) nominal default 25 (tcase), vddq=1.8v, typical process. b) minimum t oper (max) , vddq=1.7v, slow-slow process. c) maximum 0 (tcase), vddq=1.9v, fast-fast process
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 63 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. full strength default pull up driver characteristics voltage (v) minimum (23.4 ohms) normal default low (18 ohms) normal default high (18 ohms) maximum (12.6 ohms) 0.0 0.00 0.00 0.00 0.00 0.1 -4.30 -5.65 -5.90 -7.95 0.2 -8.60 -11.30 -11.80 -15.90 0.3 -12.90 -16.50 -16.80 -23.85 0.4 -16.90 -21.20 -22.10 -31.80 0.5 -20.05 -25.00 -27.60 -39.75 0.6 -22.10 -28.30 -32.40 -47.70 0.7 -23.27 -30.90 -36.90 -55.55 0.8 -24.10 -33.00 -40.90 -62.95 0.9 -24.73 -34.50 -44.60 -69.55 1.0 -25.23 -35.50 -47.70 -75.35 1.1 -25.65 -36.10 -50.40 -80.35 1.2 -26.02 -36.60 -52.60 -84.55 1.3 -26.35 -36.90 -54.20 -87.95 1.4 -26.65 -37.10 -55.90 -90.70 1.5 -26.93 -37.40 -57.10 -93.00 1.6 -27.20 -37.60 -58.40 -95.05 1.7 -27.46 -37.70 -59.60 -97.05 1.8 - -37.90 -60.90 -99.05 1.9 - - - -101.05 the driver characteristics evaluation conditions are: nominal default 25 (tcase) , vddq = 1.8 v, typical process minimum toper(max.), vddq = 1.7v, slow-slow process maximum 0 (tcase). vddq = 1.9 v, fast-fast process
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 64 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 65 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. full strength default pull down driver characteristics voltage (v) minimum (23.4 ohms) normal default low (18 ohms) normal default high (18 ohms) maximum (12.6 ohms) 0.0 0.00 0.00 0.00 0.00 0.1 4.30 5.65 5.90 7.95 0.2 8.60 11.30 11.80 15.90 0.3 12.90 16.50 16.80 23.85 0.4 16.90 21.20 22.10 31.80 0.5 20.05 25.00 27.60 39.75 0.6 22.10 28.30 32.40 47.70 0.7 23.27 30.90 36.90 55.55 0.8 24.10 33.00 40.90 62.95 0.9 24.73 34.50 44.60 69.55 1.0 25.23 35.50 47.70 75.35 1.1 25.65 36.10 50.40 80.35 1.2 26.02 36.60 52.60 84.55 1.3 26.35 36.90 54.20 87.95 1.4 26.65 37.10 55.90 90.70 1.5 26.93 37.40 57.10 93.00 1.6 27.20 37.60 58.40 95.05 1.7 27.46 37.70 59.60 97.05 1.8 - 37.90 60.90 99.05 1.9 - - - 101.05 the driver characteristics evaluation conditions are: nominal default 25 (tcase) , vddq = 1.8 v, typical process minimum toper(max.), vddq = 1.7v, slow-slow process maximum 0 (tcase). vddq = 1.9 v, fast-fast process
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 66 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. calibrated output driver v-i characteristics ddr2 sdram output driver characteristics are defined for full strength calibrated op eration as selected by the procedure outlined in the off-chip driver (ocd) impeda nce adjustment. the following tables sh ow the data in tabular format suitable for input into simulation tools. the nominal points represent a device at exactly 18 ohms. the nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohms step si ze with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guarant eed by specification). real system calibration error needs to be added to these values. it must be understood that these v-i curves are represented here or in supplier ibis models need to be adjusted to a wider ran ge as a result of any system ca libration error. since this a system specific phenomena, it cannot be quantified here. the va lues in the calibrated tabl es represent just the dram portion of uncertainty while looking at one dq only. if the calib ration procedure is used, it is possible to cause the device t o operate outside the bounds of the default device characteristics tables and figure. in such a situation, the timing parameters in the specification cannot be guaranteed. it is solely up to the system applic ation to ensure that t he device is calibrated between the minimum and maximum default values at all time s. if this can?t be guaranteed by the system calibration procedure, re-calibration policy and uncertainty with dq to dq variation, it is recommend that only the default values to be used. the nominal maximum ad minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from t he nominal condition to the maximum and mi nimum conditions. if calibrated at an extreme condition, the amount of variation could be as much as from the no minal minimum to the nominal maximum or vice versa.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 67 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. full strength calibrated pull down driver characteristics ? voltage (v) nominal minimum (21 ohms) normal low (18.75 ohms) nominal (18 ohms) normal high (17.25 ohms) nominal maximum (15 ohms) ? 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 the driver characteristics evaluation conditions are: nominal 25 (tcase) , vddq = 1.8 v, typical process nominal low and nominal high 25 (tcase), vddq = 1.8v, any process nominal minimum toper(max), vddq = 1.7 v, any process nominal maximum 0 (tcase), vddq = 1.9 v, any process full strength calibrated pull up driver characteristics voltage (v) nominal minimum (21 ohms) normal low (18.75 ohms) nominal (18 ohms) normal high (17.25 ohms) nominal maximum (15 ohms) 0.2 -9.5 -10.7 - 11.4 -11.8 -13.3 0.3 -14.3 -16.0 - 16.6 -17.4 -20.0 0.4 -18.7 -21.0 - 21.6 -23.0 -27.0 the driver characteristics evaluation conditions are: nominal 25 (tcase) , vddq = 1.8 v, typical process nominal low and nominal high 25 (tcase), vddq = 1.8v, any process nominal minimum toper(max), vddq = 1.7 v, any process nominal maximum 0 (tcase), vddq = 1.9 v, any process
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 68 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. ? -3c/3ci -ac/aci/-acl -be -bd symbol parameter min. max. min. max. min. max. min. max. units cck input capacitance, ck and ck 1.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 pf cdck input capacitance delta, ck and ck - 0.25 - 0.25 - 0.25 - 0.25 pf ci input capacitance, all other input-only pins 1.0 2.0 1.0 1.75 1.0 1.75 1.0 1.75 pf cdi input capacitance delta, all other input -only pins - 0.25 - 0.25 - 0.25 - 0.25 pf cio input/output capacitance, dq, dm, dqs, dqs 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 pf cdio input/output capacitance delta, dq, dm, dqs, dqs - 0.5 - 0.5 - 0.5 - 0.5 pf
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 69 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. power & ground clamp v-i characteristics power and ground clamps are provided on address (a0~a13, ba0, ba1, ba2), ras , cas , cs , we, cke, and odt pins. the v-i characteristics for pins with clamps is shown in the following table voltage across clamp (v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0.0 0.0 0.1 0.0 0.0 0.2 0.0 0.0 0.3 0.0 0.0 0.4 0.0 0.0 0.5 0.0 0.0 0.6 0.0 0.0 0.7 0.0 0.0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 70 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. idd specifications and measurement conditions idd specifications (vddq = 1.8v 0.1v; vdd = 1.8v 0.1v) symbol parameter/condition i/o -3c/-3ci -ac/-aci -acl -be -bd unit notes idd0 operating current x4/x8 x16 65 100 70 115 - 115 84 138 84 138 ma 1,2 idd1 operating current x4/x8 x16 75 120 85 130 - 130 102 156 102 156 ma 1,2 idd2p precharge power-down current all 9 9 9 9 9 ma 1,2 idd2n precharge standby current x4/x8 x16 30 50 40 65 - 65 48 78 48 78 ma 1,2 idd2q precharge quiet standby current x4/x8 x16 30 50 35 60 - 60 42 72 42 72 ma 1,2 mrs(12)=0 all 25 30 30 36 36 ma 1,2 idd3p active power-down standby current mrs(12)=1 all 10 10 10 11 11 ma 1,2 idd3n active standby current x4/x8 x16 45 65 50 75 - 75 60 90 60 90 ma 1,2 idd4r operating current burst read x4/x8 x16 100 150 120 235 - 235 144 282 144 282 ma 1,2 idd4w operating current burst write x4/x8 x16 100 150 120 235 - 235 144 282 144 282 ma 1,2 idd5b burst auto-refresh current x4/x8 x16 160 200 175 210 - 210 210 252 210 252 ma 1,2 idd5d distributed auto-refresh current all 15 15 15 16 16 ma 1,2 idd6 self-refresh current for standard products x4/x8 x16 9 9 9 9 - 6 9 9 9 9 ma 1,2 idd7 operating current x4/x8 x16 210 260 250 330 - 330 300 396 300 396 ma 1,2
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 71 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. idd measurement conditions (v ddq = 1.8v 0.1v; vdd = 1.8v 0.1v) idd1 operating current - one bank active - read - precharge iout = 0 ma; bl = 4, tck = tckmin, trc = trcmin; tras = trasmin; trcd = trcdmin, cl = clmin.;al = 0; cke is high, cs is high between valid commands;address bus inputs are switching,data bus inputs are switching; idd2p precharge power-down current: all banks idle; cke is low; tck = tckmin.; other control and address inputs are stable, data bus inputs are floating. idd2n precharge standby current: all banks idle; cs is high; cke is high; tck = tckmin.; other control and address bus inputs are swichting; data bus inputs are switching. idd2q precharge quiet standby current:all banks idle; cs is high; cke is high; tck = tckmin.; other control and address bus inputs are stable; data bus inputs are floating. idd3p(0) active power-down current: all banks open; tck = tckmin.;cke is low; other control and address inputs are stable; data bus inputs are floating. mr s a12 bit is set to "0"( fast power-down exit); idd3p(1) active power-down current: all banks open; tck = tckmin.;cke is low; other control and address inputs are stable; data bus inputs are floating. mr s a12 bit is set to "1"( slow power-down exit); idd3n active standby current: all banks open; tck = tckmin.; tras = trasmax.; trp = trpmin., cke is high; cs is high between valid commands; other control and address inputs are switching; data bus inputs are switching. idd4r operating current - burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = clmin.; tck = tckmin.; tras = trasmax., trp = trpmin., cke is high, cs is high between valid commands; address inputs are switching; data bus inputs are switching; iout = 0ma. idd4w operating current - burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = clmin.; tck = tckmin.; tras = trasmax., trp = trpmin.;cke is high, cs is high between valid commands; address inputs are switching; data bus inputs are switching. idd5b burst auto-refresh current: tck = tckmin.; refr esh command every trfc = trfcmin interval; cke is high, cs is high between valid commands; other control and adress inputs are switching; data bus i t switching idd5d distributed auto-refresh current: tck = tckmin.; re fresh command every trefi interval; cke is high, cs is high between valid commands; other control and adress inputs are switching; data bus inputs switching idd6 self-refresh current: cke <= 0.2v; external clock off, ck and ck at 0v; other control and address inputs are floating; data bus inputs are floating. idd7 operating bank interleave read current: 1. all bank interleaving reads; iout = 0 ma, bl =4, cl = clmin., al = trcdmin. - 1*tck; tck = tckmin., trc = trcmin.; trrd = trrdmin; trcd = 1*tck, cke = high, cs is high between valid commands; address bus inputs are stable during deselects. 2. timing pattern: - ddr2 -667 5-5-5: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d - ddr2 -800 5-5-5: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d - ddr2 -1066 6-6-6: a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d d d d 3. legend : a=activate, ra=read with auto-precharge, d=deselect 1. idd specifications are tested after the device is properly initialized. 2. idd parameter are specified with odt disabled. 3. data bus consists of dq, dm, dqs, dqs, rdqs, rdqs, ldqs, ldqs, udqs and udqs. 4. definitions for idd : low is defined as vin <= vilac(max.); high is defined as vin >= vihac(min.); stable is defined as inputs are stable at a high or low level floating is defined as inputs are vref = vddq / 2 switching is defined as: inputs are changing between high and low every other clock (once per two clocks) for adress and control signals, and inputs changing between high and low every other clock (once per two clocks) for dq signals not including mask or strobes 5. timing parameter minimum and maximum values for idd current measurements are defined in the following table.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 72 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. idd measurement conditions (cont?d) for testing the idd parameters, the following timing parameters are used: parameter symbol -3c/-3ci -ac/-aci/-acl -be -bd units latency cl 5 5 7 6 tck(avg) clock cycle time tck 3 2.5 1.875 1.875 ns active to read or write delay trcd 15 12.5 13.125 11.25 ns active to active / auto-refresh command period trc 60 57.5 58.125 56.25 ns x8 7.5 7.5 7.5 7.5 active bank a to active bank b command delay x16 trrd 10 10 10 10 ns trasmin 45 45 45 45 active to precharge command trasmax 70000 70000 70000 70000 ns precharge command period trp 15 12.5 13.125 11.25 ns refresh parameters parameter symbol component type 1gb unit auto-refresh to active / auto-refresh command period trfc all 127.5 ns (0 Q tcase Q 85 ) 7.8 standard grade (85 Q tcase Q 95 ) 3.9 s average periodic refresh interval trefi industry grade (-40 Q tcase Q 95 ) 7.8 s
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 73 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. electrical characteris tics & ac timing - absolute specification timing parameter by speed grade (vddq = 1.8v 0.1v; v dd = 1.8v 0.1v) -3c/-3ci -ac/-aci/-acl -be -bd symbol parameter min. max. min. max. min. max. min. max. units tck(avg) clock cycle time, cl=x, (average) 3000 8000 2500 8000 1875 8000 1875 8000 ps tch(avg) ck, ck high-level width (average) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tck(avg) tcl(avg) ck, ck low-level width (average) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tck(avg) wl write command to dqs associated clock edge rl-1 nck tdqss dqs latching rising transitions to associated clock edges -0.25 0.25 -0.25 0.25 -0.25 0.25 -0.25 0.25 tck(avg) tdss dqs falling edge to ck setup time 0.2 - 0.2 - 0.2 - 0.2 - tck(avg) tdsh dqs falling edge hold time from ck 0.2 - 0.2 - 0.2 - 0.2 - tck(avg) tdqsl,h dqs input low (high) pulse width 0.35 - 0.35 - 0.35 - 0.35 - tck(avg) twpre write preamble 0.35 - 0.35 - 0.35 - 0.35 - tck(avg) twpst write postamble 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck(avg) tis address and control input setup time 200 - 175 - 125 - 125 - ps tih address and control input hold time 275 - 250 - 200 - 200 - ps tipw address and control input pulse width (each input) 0.6 - 0.6 - 0.6 - 0.6 - tck(avg) tds dq and dm input setup time differential 100 - 50 - 0 - 0 - ps tdh dq and dm input hold time differential 175 - 125 - 75 - 75 - ps
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 74 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. ? -3c/-3ci -ac/-aci/-acl -be -bd symbol parameter min. max. min. max. min. max. min. max. units tdipw dq and dm input pulse width (each input) 0.35 - 0.35 - 0.35 - 0.35 - tck(avg) tac dq output access time from ck / ck -450 450 -400 400 -350 350 -350 350 ps tdqsck dqs output access time from ck / ck -400 400 -350 350 -350 350 -350 350 ps thz data-out high-impedance time from ck / ck - tac,max - tac,max - tac,max - tac,max ps tlz(dqs) dqs( dqs ) low-impedance time from ck / ck tac,min tac,max tac,min tac,max tac,min tac,max tac,min tac,max ps tlz(dq) dq low-impedance time from ck / ck 2 x tac,min tac,max 2 x tac,min tac,max 2 x tac,min tac,max 2 x tac,min tac,max ps tdqsq dqs-dq skew (for dqs & associated dq signals) - 240 - 200 - 175 - 175 ps thp clock half period min (tch (avg) tcl (avg) ) - min (tch (avg) tcl (avg) ) - min (tch (avg) tcl (avg) ) - min (tch (avg) tcl (avg) ) - ps tqhs data hold skew factor - 340 - 300 - 250 - 250 ps tqh data output hold time from dqs thp - tqhs - thp - tqhs - thp - tqhs - thp - tqhs - ps trpre read preamble 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck(avg) trpst read postamble 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck(avg) for 1kb page size (x4,x8) 7.5 - 7.5 - 7.5 - 7.5 - trrd active bank a to active bank b command period for 2kb page size (x16) 10 - 10 - 10 - 10 - ns for 1kb page size (x4,x8) 37.5 - 35 - 35 - 35 - tfaw four activate window for 2kb page size (x16) 50 - 45 - 45 - 45 - ns tccd cas a to cas b command period 2 - 2 - 2 - 2 - nck twr write recovery time 15 - 15 - 15 - 15 - ns
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 75 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. ? -3c/-3ci -ac/-aci/-acl -be -bd symbol parameter min. max. min. max. min. max. min. max. units tdal auto-precharge write recovery + precharge time wr + tnrp - wr + tnrp - wr + tnrp - wr + tnrp - nck twtr internal write to read command delay 7.5 - 7.5 - 7.5 - 7.5 - ns trtp internal read to precharge command delay 7.5 - 7.5 - 7.5 - 7.5 - ns tcke cke minimum high and low pulse width 3 - 3 - 3 - 3 - nck txsnr exit self-refresh to non-read command trfc + 10 - trfc + 10 - trfc + 10 - trfc + 10 - ns txsrd exit self-refresh to read command 200 - 200 - 200 - 200 - nck txp exit precharge power-down to any valid command (other than nop or deselect) 2 - 2 - 3 - 3 - nck txard exit power down to any valid command (other than nop or deselect) 2 - 2 - 3 - 3 - nck txards exit active power-down mode to read command (slow exit, lower power) 7-al - 8-al - 10-al - 10-al - nck taond odt turn-on delay 2 2 2 2 2 2 2 2 nck taon odt turn-on tac,min tac, max + 0.7 tac,min tac, max + 0.7 tac,min tac, max + 2.575 tac,min tac, max + 2.575 ns taonpd odt turn-on (power-down mode) tac,min + 2 2 x tck (avg) + tac, max + 1 tac,min + 2 2 x tck (avg) + tac, max + 1 tac,min + 2 2 x tck (avg) + tac, max + 1 tac,min + 2 2 x tck (avg) + tac, max + 1 ns taofd odt turn-off delay 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 nck taof odt turn-off tac,min tac, max + 0.6 tac,min tac, max + 0.6 tac,min tac, max + 0.6 tac,min tac, max + 0.6 ns
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 76 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. ? -3c/-3ci -ac/-aci/-acl -be -bd symbol parameter min. max. min. max. min. max. min. max. units taofpd odt turn-off (power-down mode) tac,min + 2 2.5 x tck (avg) + tac, max + 1 tac,min + 2 2.5 x tck (avg) + tac, max + 1 tac,min + 2 2.5 x tck (avg) + tac, max + 1 tac,min + 2 2.5 x tck (avg) + tac, max + 1 ns tanpd odt to power down entry latency 3 - 3 - 2.5 2.5 nck taxpd odt power down exit latency 8 - 8 - 11 - 11 - nck tmrd mode register set command cycle time 2 - 2 - 2 - 2 - nck tmod mrs command to odt update delay 0 12 0 12 0 12 0 12 ns toit ocd drive mode output delay 0 12 0 12 0 12 0 12 ns tdelay minimum time clocks remain on after cke asynchronously drops low tis + tck (avg) + tih - tis + tck (avg) + tih - tis + tck (avg) + tih - tis + tck (avg) + tih - ns
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 77 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. reference loads, setup & hold timing definition and slew rate derating ? reference load for timing measurements the figure represents the timing reference load used in defini ng the relevant timing parameters of the device. it is not intended to either a precise representation of the typical system environment or a de piction of the actual load presented by a production tester. system designers should use ibis or ot her simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their produc tion test conditions, generally a coaxial transmission line terminated at the tester electronics. this reference load is also used for output slew rate characterization. ? the output timing reference voltage level for singl e ended signals is the cross point with vtt. the output timing reference voltage level for differential si gnals is the cross point of the true (e.g. dqs) and the complement (e.g. dqs ) signal.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 78 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. slew rate measurements output slew rate with the reference load for timing measurements output slew rate for falling and rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals. for differential signals (e.g. dqs / dqs ) output slew rate is measured between dqs - dqs = - 500 mv and dqs - dqs = + 500 mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. input slew rate - differential signals input slew rate for differential signals (ck / ck , dqs / dqs , rdqs / rdqs ) for rising edges are measured from ck - ck = -250 mv to ck - ck = + 500 mv and from ck - ck = +250 mv to ck - ck = - 500mv for falling edges. input slew rate - single ended signals input slew rate for single ended signals (other than tis, tih, tds and tdh) are measured from dc-level to ac-level: vref -125 mv to vref + 250 mv for rising edges and from vref + 125 mv to vref - 250 mv for falling edges. for slew rate definition of the input and dat a setup and hold parameters see section 8.3 of this datasheet. input and data setup and hold time timing definition for input setup (t is ) and hold time (t ih ) address and control input setup time (t is ) is referenced from the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal applied to the device under test. addr ess and control input hold time (tih) is referenced from the input signal crossing at the v il (dc) level for a rising signal and v ih (dc) for a falling signal applied to the device under test v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss t is t ih t is t ih ck ck ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 79 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. timing definition for data setup (t ds ) and hold time (t dh ) v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss t ds t dh t ds v ref t dh dqs dqs dqs differential input waveform single-ended input waveform ? 1. data input setup time with differential data strobe enabled mr [bit10] =0, is referenced from the input signal crossing at the vih (ac) level to the differential data strobe cross point for a rising signal, and from the input signal crossing at the v il (ac) level to differential data strobe cross point for a falling signal applied to the device under test. input waveform timing with single-ended data strobe enabled mr [bit10] =1, is referenced from the input signal crossing at the vih (ac) level to the data strobe crossing vref for a rising signal, and from the input signal cr ossing at the vil (ac) leve l to the single-ended dat a strobe crossing vref for a falling signal applied to the device under test. 2. data input hold time with differential data strobe enabled mr [bit10]=0, is referenced from the input signal crossing at the vil(dc) level to the differential data str obe cross point for a rising signal and vih( dc) to the differential data strobe cross point for a falling signal applied to the device under test. i nput waveform timing with single-ended data strobe enabled mr[bit10]=1, is referenced from the input signal crossing at the vil(dc) level to the single-ended data strobe crossing vref for a rising signal and vih(dc) to the single-ended data strobe crossing vref for a falling signal applied to the device under test
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 80 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. slew rate definition for input and data setup and hold times setup (tis & tds) nominal slew rate for a rising signal is defin ed as the slew rate between the last crossing of vih(dc)min and the first crossing of vih(ac)min. setup (tis & tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vil(dc)max and t he first crossing of vil(ac)max, (fig. a) if the actual signal is always earlier than the nominal slew rate line between shaded ?dc to ac region? , use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded ?dc to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.(fig.b) hold (tih & tdh) nominal slew rate for a rising signal is defin ed as the slew rate between t he last crossing of vil (dc) max and the first crossing of vref. hold (tih & tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first cr ossing of vref.(fig. a). if the actual si gnal is always later than the nominal slew rate line between shaded ?dc to vref region?, use nominal slew rate for derating value. if the actual signal is earlier than th e nominal slew rate line anywhere between shaded ?dc to vref region ?, the slew rate of a tangent line to the actual signal from the dc level to vref level is used for derating value.(fig.b) v ss v il(ac) max v il(dc) max v ref v ih(dc) min v ddq v ih(ac) min delta tfs delta trh delta tfh delta trs t s t h t s t h dc to ac region dc to ac region dc to vref region dc to vref region
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 81 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. v ss v il(ac) max v il(dc) max v ref v ih(dc) min v ddq v ih(ac) min delta tfs delta trh delta tfh delta trs t s t h t s t h dc to ac region dc to ac region dc to vref region dc to vref region setup slew rate = vil(dc)max - vil(ac)max delta t fs falling signal setup slew rate = vih( dc)mi n - vil( ac)mi n delta t rs rising signal hold slew rate = vref - vil(dc)max delta t rh rising signal hold slew rate = vih( dc)mi n - vref delta t fh falling signal setup slew rate = tangent line [vil(dc)max - vil(ac)max] delta t fs setup slew rate = tangent line [vih(dc)min - vil(ac)min] delta trs hold slew rate = tangent line [ref - vil(dc)max] delta trh hold slew rate = tangent line [vih(dc)min - vr ef] delta tfh falling signal falling signal ri si ng signal ri si ng signal
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 82 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. input setup (t is ) and hold (t ih ) time derating table ck, ck differential slew rate (-3c/-3ci/-ac/-aci/-acl/-be/-bd) 2.0 v/ns 1.5 v/ns 1.0 v/ns d tis d tih d tis d tih d tis d tih units 4.00 150 94 180 124 210 154 ps 3.50 143 89 173 119 203 149 ps 3.00 133 83 163 113 193 143 ps 2.50 120 75 150 105 180 135 ps 2.00 100 45 130 75 160 105 ps 1.50 67 21 97 51 127 81 ps 1.00 0 0 30 30 60 60 ps 0.90 -5 -14 25 16 55 46 ps 0.80 -13 -31 17 -1 47 29 ps 0.70 -22 -54 8 -24 38 6 ps 0.60 -34 -83 -4 -53 26 -23 ps 0.50 -60 -125 -30 -95 0 -65 ps 0.40 -100 -188 -70 -158 -40 -128 ps 0.30 -168 -292 -138 -262 -108 -232 ps 0.25 -200 -375 -170 -345 -140 -315 ps 0.20 -325 -500 -295 -470 -265 -440 ps 0.15 -517 -708 -487 -678 -457 -648 ps command/address slew rate (v/ns) 0.10 -1000 -1125 -970 -1095 -940 -1065 ps
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 83 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. data setup (tds) and hold time (tdh) derating table dqs, dqs differential slew rate (-3c/-3ci/-ac/-aci/-acl/-be/-bd) 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh 2.0 100 45 100 45 100 45 - - - - - - - - - - - - 1.5 67 21 67 21 67 21 79 33 - - - - - - - - - - 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - 0.9 - - -5 -14 -5 -14 7 -2 19 10 31 22 - - - - - - 0.8 - - - - -13 -31 -1 -19 11 -7 23 5 35 17 - - - - 0.7 - - - - - - -10 -42 2 -30 14 -18 26 -6 38 6 - - 0.6 - - - - - - - - -10 -59 2 -47 14 -35 26 -23 38 -11 0.5 - - - - - - - - - - -24 -89 -12 -77 0 -65 12 -53 dq slewrate (v/ns) 0.4 - - - - - - - - - - - - -52 -140 -40 -128 -28 -116 1. all units in ps. 2. for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the individual datashe et value to the derating value listed in the previous table
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 84 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. overshoot and undershoot specification ac overshoot / undershoot specification for address and control pins parameter -3c/-3ci -ac/-aci/-acl -be -bd units maximum peak amplitude allowed fo r overshoot area 0. 5 0.5 0.5 0.5 v maximum peak amplitude allowed fo r undershoot area 0. 5 0.5 0.5 0.5 v maximum overshoot area abov e vdd 0.8 0.66 0.66 0.66 v-ns maximum undershoot area belo w vss 0.8 0.66 0.66 0.66 v-ns vdd vss overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v) ac overshoot / undershoot specification for clock, data, strobe and mask pins parameter -3c/-3ci -ac/-aci/-acl -be -bd units maximum peak amplitude allowed fo r overshoot area 0. 5 0.5 0.5 0.5 v maximum peak amplitude allowed fo r undershoot area 0. 5 0.5 0.5 0.5 v maximum overshoot area abov e vdd 0.23 0.23 0.23 0.23 v-ns maximum undershoot area belo w vss 0.23 0.23 0.23 0.23 v-ns vddq vssq overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v) ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 85 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. package dimensions (x4/x8; 60 balls; bga package) 10.00 +/- 0.10 0.80 8.00 ?
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 86 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. package dimensions (x16; 84 balls; bga package) note : all dimensions are typical unless otherwise stated . 12.50 +/- 0.10 0 . 40 max . 0. 25 min. 1. 20 max . 84 ball bga 0.80 11. 20 dia . min 0.40 max 0.50 unit : millimeters min 0.10 min 0.10 0. 80 6. 40 8.00+/-0.10 pin a1 index 0. 10 max.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 87 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. revision log rev date modification 0.1 11/2009 preliminary release 1.0 12/2009 offi cial release 1.1 5/2010 modified the typo on the page 8 1.2 5/2010 added the timing s pecificity of ddr2-1066 (-be) 1.3 6/2010 modified the typos on the page 1 and the page 76. 1.4 7/2010 updated the id d values on the page 71. 1.5 8/2010 added the part num ber of be on the page 8. 1.6 9/2010 modified the timing values of trc (min), trp (min) and trcd (min) for be on the page 1 and added the timing of tfaw for 2kb package size on the page 74. 1.7 9/2010 added the timing of trrd for 2kb package size on the page 74. 1.8 10/2010 added a new part number of nt5tu64m16gg-acl on the page 8 and modified idd6 < 6 ma for nt5tu64m16gg-acl on the page 70.
nt5tu256m4ge / nt5tu128m8ge / nt5tu64m16gg 1gb ddr2 sdram ???????????????????? 88 ? rev 1.8 consumer dram october / 2010 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to ch ange products and specif ications without notice. ? ? nanya technology corporation. all rights reserved. printed in taiwan, r.o.c., 2006 the following are trademarks of nanya technology corp oration in r.o.c, or other countries, or both. nanya and nanya logo other company, product and service names ma y be trademarks or service marks of others. nanya technology corporation (ntc) reserves the ri ght to make changes without notice. ntc warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with ntc?s standard warranty. testing and other qu ality control techniques ar e utilized to the extent ntc deems necessary to support this warranty. specific testing of all par ameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (?critical applications?). ntc semiconductor products are not designed, intend, authorized, or warranted to be suitable for use in life-support application s, devices or systems or other critical applications. inclusion of ntc products in such applications is understood to be fully at the risk of the cu stomer. use of ntc products in such applications requires the written approval of an appropr iate ntc officer. question concerning potential risk applications should be directed to ntc through a local sales office. in order to minimize risks associated with the customer?s applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or proc edural hazards.ntc assumes no liability of applications assistance, customer product design, soft ware performance, or infringement of pat ents or services described herein. nor does ntc warrant or represent that any li cense, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual pro perty right of ntc covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. nanya technology corporation hwa ya technology park, 669, fu hsing 3rd rd., kueishan, taoyuan, taiwan, r.o.c. the nanya technology corporation home page can be found at http:\\www.nanya.com

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